These limits are not the same at the input and output sides. Manufacturers specify voltage limits to represent the logical 0 or 1. See below Figure to calculate noise margin It is generally supplied by the manufacturers in the form of a curve between noise margin and noise pulse width. This is referred to as ac noise margin and is substantially greater than the dc noise margin. This means that a logic circuit can effectively tolerate a large noise amplitude if the noise is of a very short duration. Under this condition, a large pulse amplitude would be required to produce a change in the circuit output. As the noise pulse width decreases and approaches the propagation delay time of the circuit, the pulse duration is too short for the circuit to respond. as far as the response of the logic circuit is concerned. For high speed ICs, a pulse width of a few microseconds is extremely long in comparison to the propagation delay time of the circuit and therefore, treated as d.c. Strictly speaking, the noise is generally thought of as an a.c. The noise margins defined above are referred to as dc noise margins. The circuit's ability to tolerate noise signals is referred to as the noise immunity, a quantitative measure of which is called noise margin. This may cause the voltage at the input to a logic circuit to drop below VIH or rise above VIL and may produce undesired operation. Stray electric and magnetic fields may induce unwanted voltages, known as noise, on the connecting wires between logic circuits. Definition: Ability of the gate to tolerate fluctuations of the voltage levels.The input and output voltage levels defined above point.
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